From the Research Universities edition of September 29, 2026
AlphaFold2 on Cloud TPU v5e: 0.47 s/chip vs 13.1 s T4, but default path uses 1 of 8 chips; pmap 6.5–7.9×
Stanford Summer Session / LUISS Guido Carli / Al Akhawayn University — arXiv preprint · Higher education research computing / scientific AI workloads (protein structure inference) · United States (Stanford TPU access; Colab baselines); transferable methods with cloud-tenancy limits
- Publisher
- arXiv 2609.34818
- Original publication
- September 28, 2026 (arXiv; revised September 29, 2026 v2)
- Source retrieved
- 2026-09-30
What happened
Pazienza and El Bani measure identical AlphaFold2 inference code on Colab CPU, NVIDIA T4 GPU, and an eight-chip Cloud TPU v5e slice. Steady-state single-chip TPU time is 0.47 s/call versus 13.1 s on T4 in the August campaign (~27.8×), but the default path places work on only one of eight billed chips. jax.vmap never exceeds single-query throughput; jax.pmap yields 6.5–7.9× eight-over-one-chip throughput on a matched length grid. Automatic sharding leaves per-chip footprint unchanged (consistent with replication). About three quarters of a traced first-call span is JAX tracing/compilation. September Colab reruns did not reproduce August CPU/GPU baselines (~1.6–2× drift), so hardware ratios are campaign-specific. Paper revised 29 Sep 2026 (v2).
Why it matters
Campus research-computing and AI-for-science programs buying accelerators need evidence that software mapping, compilation caching, and multi-device programming—not device choice alone—determine realized scientific throughput and cost.
Evidence and measured results
arXiv abs/html 2609.34818 opened via HTTPS (curl UA SLED-research-bot/1.0); steady-state timings, idle-chip finding, pmap/vmap results, compilation share, and cross-session variability taken from opened abstract and paper body (submitted 28 Sep 2026; revised 29 Sep 2026).
Limitations and uncertainty
Preprint; untrained AlphaFold2 weights for timing; mostly single TPU runs; August baselines partially unreproducible; T4 vs v5e not a campus GPU-cluster comparison; AlphaFold3 release tested lacks TPU backend.
Put this evidence to work
Lighthouse Advisory interpretation, grounded in this source. Enriched 2026-09-29; this does not change the original publication date. Each role follows the same checklist so takeaways compare across sources.
Sales
Role takeaway
- Customer problem
- Scientific AI inference buyers risk paying for multi-chip accelerators while software paths leave most chips idle.
- Stakeholders
- Research computing / HPC directors
- VPR / computational science leads
- PI structural-biology groups
- Cloud/finops for research
- Platform engineering
- Discovery questions
- How many chips does the default job actually use (device memory nonzero)?
- Are cold-start compilation costs amortized for the workload mix?
- Is cost modeled per busy chip or per billed slice?
- Can baselines be reproduced across sessions with pinned environments?
- Value hypothesis
- Explicit multi-device mapping and compilation caching can convert accelerator CapEx into measured scientific inference throughput when default paths leave chips idle.
- Potential engagement
- Two-week AlphaFold-class benchmark on target accelerators with single-chip, pmap, and cost-per-1k-prediction reports.
- Unsupported claims
- Guaranteed 27.8× over every campus GPU
- Automatic sharding always splits AlphaFold2
- Stable cloud Colab baselines
- AlphaFold3 TPU portability
Pre-sales engineering
Role takeaway
- Fit
- JAX/XLA scientific inference on multi-chip TPU/GPU with explicit device mapping and compilation cache.
- Architecture and integration
- Wire jit + pmap entry points, per-device HBM telemetry, persistent compilation cache, and pinned dependency lockfiles into the research workflow.
- Prerequisites
- Pinned JAX/Haiku stack
- Shape-stable input policy
- Multi-device allocator
- Environment/provenance capture
- Cost telemetry per chip-hour
- Constraints
- Unannotated models may replicate
- Cold-start compilation dominance
- Cloud tenancy variability
- Preprint/single-campaign ratios
- Security
- Capture and retain run environments; avoid leaking research credentials via notebook sharing; treat cloud host reassignment as an audit risk for timing claims.
- Proof of value
- Steady-state time/chip with chips-in-use
- pmap speedup on matched grid
- Cold/steady ratio with/without cache
- Cost per 1k predictions at busy vs idle allocation
Delivery
Role takeaway
- Work
- Implement benchmark harness, pin environments, run single/multi-device campaigns, publish cost and chips-in-use dashboards.
- Dependencies
- Accelerator allocation
- JAX scientific app owners
- Storage for traces/results
- Finops/cost APIs
- Ownership
- Research computing owns pools and billing interpretation; app teams own model parallelism annotations; PIs own scientific validity of structures.
- Skills and adoption
- Train users to check device memory across chips and prefer pmap/annotated sharding over assuming automatic split.
- Governance checkpoints
- Environment pin freeze
- Benchmark protocol review
- Cost-model sign-off
- Reproducibility rerun gate
- Acceptance criteria
- Documented chips-in-use ≥ N for billed jobs
- Published cold and steady timings
- Matched-grid multi-device report
- Risks
- Idle billed capacity
- Unreproducible baselines
- Overfit to one sequence length
- Missing sharding annotations
Implementation considerations
Lighthouse Advisory interpretation across the operating dimensions a public-sector buyer must settle before this evidence becomes a design. Each note answers the question under its heading for this specific source.
Architecture and integration
What must connect, and where does the AI sit in the workflow?
Treat JAX/XLA compilation caches, explicit pmap/device mapping, and sharding annotations as first-class architecture for scientific JAX workloads; default jit paths may leave multi-chip slices mostly idle while still billing the pod.
Governance
Who approves, reviews and stays accountable for outcomes?
Publish allocation and cost models that distinguish single-chip useful work from multi-chip billed capacity; require workload-level benchmarks with stated software stack, not brochure FLOPS, before claiming research readiness.
Security and privacy
What data, permissions and controls need testing?
Cloud Colab tenancy and unpinned dependencies complicate auditability of scientific timing studies; retain environment captures and avoid treating unreproducible cloud baselines as procurement constants.
Accessibility and workforce
Who is affected, and what skills or accommodations follow?
Multi-device JAX competence becomes a workforce prerequisite; without training, researchers may under-use expensive slices while still exhausting allocations.
Procurement
What should contracts, pricing and exit terms secure?
Require workload benchmarks stating software path, chips-in-use, and cold-start behavior in accelerator RFPs; price busy useful capacity, not peak chip counts alone.
Operating model
Which teams own the service once it runs?
Operating model must include compilation-cache ops, multi-device programming support, and session-reproducible benchmarking—not only queue access to accelerators.
Publication history
- 2026-09-29Research Universities · Issue 224 resources
Stable resource ID: alphafold2-tpu-inference-software-layer-20260928